Preisvergleich auf Barfigo.de: VERIFICATION

Given the growing size and heterogeneity of Systems on Chip (SOC), the design process from initial specification to chip fabrication has become increasingly complex.
This growing complexity provides incentive for designers to use high-level languages such as C, SystemC, and SystemVerilog for system-level design.
While a major goal of these high-level languages is to enable verification at a higher level of abstraction, allowing early exploration of system-level designs, the focus so far for validation purposes has been on traditional testing techniques such as random testing and scenario-based testing.
This book focuses on high-level verification, presenting a design methodology that relies upon advances in synthesis techniques as well as on incremental refinement of the design process.
These refinements can be done manually or through elaboration tools.
This book discusses verification of specific properties in designs written using high-level languages, as well as checking that the refined implementations are equivalent to their high-level specifications.
The novelty of each of these techniques is that they use a combination of formal techniques to do scalable verification of system designs completely automatically.
The verification techniques presented in this book include methods for verifying properties of high-level designs and methods for verifying that the translation from high-level design to a low-level Register Transfer Language (RTL) design preserves semantics.
Used together, these techniques guarantee that properties verified in the high-level design are preserved through the translation to low-level RTL.

EUR 106.95

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Constraint-Based Verification covers an emerging field in functional verification of electronic designs, referred to as the constraint-based verification.  The topics are developed in the context of a wide range of dynamic and static verification approaches including simulation, emulation, and formal methods.  The goal is to show how constraints, or assertions, can be used towards automating the generation of testbenches, resulting in a seamless verification flow.  Topics such as verification coverage, and connection with assertion based verification, are also covered.

The book targets verification engineers as well as researchers.
It covers both methodological and technical issues.  Particular stress is given to the latest advances in functional verification.

The research community has witnessed recent growth of interests in constraint-based functional verification.  Various techniques have been developed.  They are relatively new, but have reached a level of maturity so that they are appearing in commercial tools such as Vera and System Verilog.

EUR 126.21

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1., st Edition.

EUR 111.80

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Functional verification has become an important aspect of the chip design process.
Significant resources, both in industry and academia, are devoted to the design complexity and verification endeavors.

SAT-Based Scalable Formal Verification Solutions discusses in detail several of the latest and interesting scalable SAT-based techniques including: Hybrid SAT Solver, Customized Bounded/Unbounded Model Checking, Distributed Model Checking, Proofs and Proof-based Abstraction Methods, Verification of Embedded Memory System & Multi-clock Systems, and Synthesis for Verification Paradigm.
These techniques have been designed and implemented in a verification platform Verisol (formally called DiVer) and have been used successfully in industry.
This book provides algorithmic details and engineering insights into devising scalable approaches for an effective realization.
It also includes the authors’ practical experiences and recommendations in verifying the large industry designs using VeriSol.

The book is primarily written for researchers, scientists, and verification engineers who would like to gain an in-depth understanding of scalable SAT-based verification techniques.
The book will also be of interest for CAD tool developers who would like to incorporate various SAT-based advanced techniques in their products.

Written for: Verification researchers and engineers, computer engineers, CAD tool developers

EUR 126.21

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One of the biggest challenges in chip and system design is determining whether the hardware works correctly.
That is the job of functional verification engineers and they are the audience for this comprehensive text from three top industry professionals.

As designs increase in complexity, so has the value of verification engineers within the hardware design team.
In fact, the need for skilled verification engineers has grown dramatically--functional verification now consumes between 40 and 70% of a projects labor, and about half its cost.
Currently there are very few books on verification for engineers, and none that cover the subject as comprehensively as this text.


A key strength of this book is that it describes the entire verification cycle and details each stage.
The organization of the book follows the cycle, demonstrating how functional verification engages all aspects of the overall design effort and how individual cycle stages relate to the larger design process.
Throughout the text, the authors leverage their 35 plus years experience in functional verification, providing examples and case studies, and focusing on the skills, methods, and tools needed to complete each verification task.
Additionally, the major vendors (Mentor Graphics, Cadence Design Systems, Verisity, and Synopsys) have implemented key examples from the text and made these available on line, so that the reader can test out the methods described in the text.

* Comprehensive overview of the complete verification cycle
* Combines industry experience with a strong emphasis on functional verification fundamentals
* Includes industry examples and real-world case studies

EUR 66.58

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